1. Field of the Invention
This invention relates to an SRAM memory array comprising memory cells with each cell containing six devices, the basic storage nodes which store the true and complement of the data are constructed from a standard four device, cross coupled flip-flop cell, and in particular to an SRAM memory array wherein one internal storage node of this cell is connected through an access pass gate to one local bit line (LBL), the second internal storage node connected in a like manner to a second LBL, each LBL connected to a limited number, e.g. sixteen to thirty-two of other similar storage cells, the two LBLs each connected to the gate of a separate read head nFET for discharging to ground one of two previously precharged global read lines so as to pass the inverse of the signal on the LBL and thus on the read head gate to a global read/write bit line.
2. Description of Background
Before our invention current six device SRAM cells were encountering significant stability problems as we scale below 0.1 microns. The main reason for this is that the device tolerances, particularly the threshold voltage variations from device to device, do not scale appropriately as the technology scales to smaller dimensions. When an SRAM cell is read, the bit lines are precharged ‘HIGH’ which places a ‘disturb’ signal on the ‘0’ node of the cross-coupled flip-flop. For the nominal design case, this ‘disturb’ signal is quite tolerable; however, if the threshold variations between devices is sufficiently large, this ‘disturb’ signal can cause some cells to flip state, i.e. a stored ‘0’ becomes a ‘1’ and vice versa. Current SRAM cell designs employ two techniques to circumvent this, 1) reduce threshold variations by making the devices, and hence cell, larger than the smallest size normal scaling rules would allow, and 2), use eight devices per cell, with the extra devices eliminating the ‘disturb’ signal during reading. Both techniques significantly increase the size of the SRAM cell and hence reduce the density, a very undesirable result.
The design of robust 6T SRAM memory is a key challenge for future microprocessor designs. It is generally agreed that the 6T SRAM design approach is broken due to various technology-scaling issues. These issues make it increasingly difficult to design 6T SRAM memories with acceptable stability, performance, power and yield with the current design approaches. What is needed is an approach that deals with each of these factors over a range of values.
As technology lithographic dimensions scale below 0.1 microns, FET device tolerances, particularly the threshold voltage variations from device to device, do not scale appropriately as they have in the past—the threshold spread between adjacent or nearby devices is increasing. As a result, SRAM cells are currently, encountering significant stability difficulties. This problem occurs as follows. A typical, standard six device (6T) SRAM cell has two internal nodes, ‘A’ and ‘B’ as shown in prior art FIG. 1A which for example store ‘0’/‘1’ respectively on the two nodes for a stored ‘0’, and the reverse of ‘1’/‘0’ respectively on the nodes for a stored ‘1’. These two nodes are coupled to a pair of balanced bit/sense lines, which are used for both reading and writing. For reading the state of the cell, both bit lines, which are connected to multiple cells, are precharged high (for example to +Vdd, the power supply voltage) through a separate device (not shown) attached to each bit line. On a ‘READ’ operation, the desired cell is connected to this precharged bit line pair by activating the word line for this desired cell. This turns ‘ON’ the two access devices, N2 and N3. As a result, the internal storage node, which happens to currently be latched at ‘0’, will see a large voltage applied to it, which is a ‘disturb’ signal. If the cross-coupled pair of nFETS N0 and N1 are identical, and likewise if the pFETs P0 and P1 are identical, the cell is stable and the read ‘disturb’ cannot cause the cell to switch states. However, if the variation in threshold voltages of the cross-coupled nFET and/or pFET devices is sufficiently large, the ‘disturb’ signal can cause this ‘0’ node to rise sufficiently ‘HIGH’ such that the cross-coupled arrangement will pull the previously ‘1’ node to ‘0’, thus reversing the stored state, a significant error.
The fundamental problem, which gives raise to the read ‘disturb’ can be understood in terms of the capacitance loading, connected to an SRAM cell during reading. An equivalent circuit for the reading of the cross-coupled 6 device SRAM cell, one example of which is illustrated in prior art FIG. 1B, is assumed to have storage node ‘B’ at ‘0’ volts initially (with node ‘A’ necessarily at Vdd volts). Currently, in state of the art SRAM design, balanced sensing is used in which a pair of (nearly) identical capacitors, C[bl] (bit line capacitance) are precharged to Vdd and then suddenly connected to nodes ‘A’ and ‘B’. A sense signal is obtained by allowing the cell to develop an offset voltage across this pair, which triggers a differential sense amp. This offset is achieved as follows:
The precharged voltage on its bit line, being already at Vdd, does not affect node ‘A’. In fact, a large ‘C’ on node ‘A’ will be helpful in holding ‘A’ at Vdd. However, node ‘B’, initially at ‘0’, now has a large capacitor, C[bl], the bit line capacitance, at voltage Vdd connected to it. The FET pull-down device, N0, must sink the charge on C[bl] to ground in order to discharge it to some low value, the offset voltage. However, device N0, even in the ‘ON’ state has a significant resistance, so the voltage from node ‘B’ to ground will increase above ‘0’. In the meantime, device N1 has its gate voltage supposedly at ‘0’ (at voltage of node ‘B’) so it is ‘OFF’, and P1 is ‘ON’, which allows node ‘A’ to remain high. However, if the threshold voltage, Vt, of device N1 just happens to be sufficiently ‘LOW’, and if node ‘B’ happens to rise sufficiently ‘HIGH’, device N1 will start to turn ‘ON’. If likewise, the threshold of N0 is higher than that of N1, it is easily turned ‘OFF’, and the feedback effect of the cross-coupled arrangement will reinforce this supposedly temporary transient swing in voltages and can cause the node voltages at ‘A’ and ‘B’ to reverse state, an error.
The culprit in this scenario is the very large bit line capacitance, which makes it difficult to hold node ‘B’ at ‘0’, plus the large tolerance spread between devices N1 and N0. Note, tolerance spreads between P1 and P0 contribute in a somewhat analogous manner. For instance, with node ‘A’ at ‘1’ and ‘B’ at ‘0’ as above, device P1 is ‘ON’ and holds node ‘A’ ‘HIGH’. If the threshold of P1 is ‘HIGH’, it will start to turn ‘OFF’ as node ‘B’ rises slightly, due to the read ‘disturb’. This will start decreasing the original ‘HIGH’ voltage at node ‘A’ as node ‘B’ is raised. If the threshold of P0 is simultaneously ‘LOW’ compared to P1, then the rising voltage on node ‘A’ will cause device P0, which was originally ‘OFF’, to begin to turn ‘ON’ which reinforces the increasing voltage on node ‘B’. This will cause the cell nodes to reverse voltage, and must be avoided.
For a given technology, the threshold variations between adjacent devices become larger as the devices approach minimum dimensions. Thus one method for improving stability is by making the device channel length and width larger, which results in lower density, an undesirable effect. If we wish to increase cell stability without increasing the cell device sizes, the bit line capacitance must be reduced without significantly increasing the effective, average cell size.